Hybrid FPGA + MC68HC000

[sporniket]

Epic

Initialisation Good

As FPGA

I want to hold the CPU on reset state as long as the system is not ready

In order to prepare the system (ROM copying etc...)

class ResetGate(Elaboratable):
    def __init__(self,reviewers:List[Signal],actualReset)
        """
        reviewers is a list of 1-bit width signals, that are emitted by subsystem requiring the reset to persist in other parts of the design. When a reviewer is ready, it emits 1. 
        """
        self.reviewers = reviewers
        self.actualReset = actualReset
        self.outReset = Signal()

    def ports():
        return self.reviewers + self.actualReset + self.outReset

    def elaborate(self, platform):
        m = Module()
        blockReset = Signal()
        m.d.comb += [
            blockReset.eq(Cat(self.reviewers).all())
        ]
        m.d.sync += [
            outReset.eq(blockReset & actualReset)
        ]
        return m

Functionnal Memory mapping

24 bits mode

reference

Range	R/W	Description
$0 (Long)	R	SSP at reset, taken from ROM $xxx
$4 (Long)	R	PC at reset, taken from ROM $xxx
$8→$00CFFFFF	RW	14 MB RAM
$xxD00000→$xxDFFFFF	?	Unreachable ?
$xxE00000→$xxEFFFFF	R	OS ROM (STe onward) ; STE : 256K only, STBook : the full 1MB
$xxF00000→$xxF0003F	?	?
$xxF00040→$xxF9FFFF	-	Should be unreachable
$xxFA0000→$xxFBFFFF	R	Cartridge ROM
$xxFC0000→$xxFEFFFF	R	OS ROM (before STe)
$xxFF0000→$xxFFFFFF	RW	Peripheral registers

SDRam Memory Map

For a SDRAM size on N, in MB.

• 0..N-2 : RAM
• N-1 : Copy of OS ROM

[sporniket]

address decoder : send a chip select on a unique port (a.k.a demux)

# 24 bits modes
class AddressDecoder24(Elaboratable):
    def __init__(self):
        self.addr = Signal(24) # plug to bus ADDR
        self.frameUp = Signal(4) # ADDR[20:24]
        self.frameLow = Signal(4) # ADDR[16:20]
        self.framePeriph = Signal(4) # ADDR[12:16]
        self.selector=Signal(xxx) # width = number of selectable subsystems

    def ports(self)->List[]:
        return [self.addr, self.selector]

    def elaborate(self,platform):
        m = Module()
        m.d.comb += [
            self.frameUp.eq(self.addr[20:24]),
            self.frameLow.eq(self.addr[20:24]),
            self.framePeriph.eq(self.addr[20:24]),
        ]
        with m.Switch(self.frameUp):
            with m.Case(0):
                 with m.If((addr[2:24]==0) | (addr[2:24]==1)):
                    m.d.sync += self.selector.eq(SELECT_ROM)
                 with m.Else():
                    m.d.sync += self.selector.eq(SELECT_RAM)
            with m.Case(0xE):
                m.d.sync += self.selector.eq(SELECT_ROM)
            with m.Case(0xF):
                # Switch case over self.frameLow, then for case 0xF switch case over self.framePeriph
                # and at the end self.selector.eq(SELECT_<whatever>)
            with m.Default():
                m.d.sync += [
                    self.selector.eq(SELECT_RAM)
                ]

        return m

[sporniket]

see https://github.com/sporniket/the-pretender-atari-ste/issues/6 and https://github.com/sporniket/the-pretender-atari-ste/issues/1