Better support for multiplication (MUL)

[spotlessmind1975]

MUL x,y can perform a sizeof(x)-unsigned-multiplication over y and always get the correct result regardless of x or y being signed. This means:

• if x is 8 bit, a 8x8->8 unsigned-mul,
• if x is 16 bits, a 16x16->16 unsigned-mul, and finally
• if x is 32 a 32x32->32 unsigned-mul.

Of couse this will require some cpu_math_mul_Nbit_to_Nbit(), which can be highly optimized in asm (it is just a single ASM instruction for the 6809 for 8bit), but can be emulated via cpu_math_mul_Nbit_to_2Nbit() + truncation as a start.

Originally posted by @Samuel-DEVULDER in https://github.com/spotlessmind1975/ugbasic/discussions/268#discussioncomment-1709981_

[Neotenien]

MUL x,y can perform a sizeof(x)-unsigned-multiplication over y and always get the correct result regardless of x or y being signed. This means:

• if x is 8 bit, a 8x8->8 unsigned-mul,
• if x is 16 bits, a 16x16->16 unsigned-mul, and finally
• if x is 32 a 32x32->32 unsigned-mul.

Of couse this will require some cpu_math_mul_Nbit_to_Nbit(), which can be highly optimized in asm (it is just a single ASM instruction for the 6809 for 8bit), but can be emulated via cpu_math_mul_Nbit_to_2Nbit() + truncation as a start.

Originally posted by @Samuel-DEVULDER in #268 (comment)_

Well it's true that the algorith for that (for 6502 and z80) osuld be a loop of shoitf and add instruction between 2 bytes.

But concerning 6809, it exiist, in effect, the MUL instruction for doing a 8x8=>16bits (AB = D register in only 11 cycles

And even many better, on tghe 6309 (a fully 6809 compatible Hitachi processor) hav a full set of16x16=> 32 bits and vice versa MUL and DIV instruction which are even better than the one on 68k processor (2 time faster oin term of cycle of timer).

[Samuel-DEVULDER]

This is not related to the topic. The topic here is to take notice that unsigned multiplications can be used in place of signed ones when only the lower half of the result is needed.