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srsran / zynq_timestamping

Open source Zynq timestamping implementation from Software Radio Systems (SRS)
https://srsran.github.io/zynq_timestamping/index.html
GNU Affero General Public License v3.0
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Add late/underlow situation reporting to the RF driver #53

Open ofontbach opened 1 year ago

ofontbach commented 1 year ago

Currently the FPGA flags late/underflow situations, but those are not forwarded to the CPU and, thus, no reporting is provided. The FPGA flags should be forwarded to the driver so as to print warnings to make the user aware of the communication bottleneck.