Submission: On-Chip Clock Multiplier (PLL) on Global Foundry 180nm CMOS

[SultanShadow]

This notebook is a submission for the IEEE SSCS "Code-a-Chip" Travel Grant 2023 in category 2. It describes the 128MHz Clock Multiplier PLL design using Global foundry 180nm open source CMOS PDK

[msaligane]

Due to multiple requests. We have decided to extend the deadline to the 25th Nov. so that, hopefully, you have enough time to review your submissions.