VHDL-2008 support

[fpgadev]

Thank you very much for your fixes on the VHDL syntax !

For your next release, would it be possible to include the following patch to support the VHDL-2008 syntax ? http://sourceforge.net/p/veditor/tickets/3/

Because the link for the compiling procedure is dead and it seems nobody has it ;-( http://sourceforge.net/p/veditor/discussion/358081/thread/7a865ab0/

Thank you in advance.

[ssharks]

Dear fpgadev,

Thanks for your patch. I applied it on the repository and can be found on the branch VHDL 2008 patch. Since I do no VHDL 2008 yet, could you test the release 1.2.15 and report if it fully works?

I also added a README.md with the how to on building the sources. I was not able to test the howto since it is already installed on my system. Could you report if this works for you or if thinks are missing or if any questions remain.

Since I'm not such a JavaCC hero, could you see if you can make the following constuction work? constant addr_len : integer := 19; constant size1 : unsigned(addr_len-1 downto 0) := (addr_len-1 => '1', others => '0'); constant size2 : unsigned(18 downto 0) := (18 => '1', others => '0'); Currently the parser falls on the line size1, while size2 is parced without any issue.

Best regards,

ssharks

[fpgadev]

Thank you very much for your reactivity in integrating the patch and writing the building readme.

First of all, I just added the link to this patch, but its creator is HorstWe.

I have been using your release 1.2.15 for 3 days. I did not notice any regression from 1.2.12 I used before. I validated the working of the new VHDL syntax on clauses 8.7, 9.2.3, 11.8, 15.8. I did not validate yet for the clauses 4.7, 4.9, 15.2 because it is more complex to test. I confirm the parser failure on the declaration of size1, while vsim reports no error, but sorry I can't help you since I never used JavaCC.

I forwarded the building readme to someone who has a better knowledge than me in the Eclipse environment and we won't miss to give you a feedback.

This patch does not cover all the VHDL-2008 enhancements, like the "all" in a process sensibility list (clause 11.3), but it is a good start ;-)

Sincerely

[btrotter]

I am thrilled to see fresh activity on veditor and particularly excited about the addition of VHDL-2008 support! However, shouldn't VHDL-1993 and VHDL-2008 syntax enforcement be kept separate? Usually, the HDL author needs to comply with a particular version of the language for a given file and/or project. For example, if a project is required to comply with VHDL-1993 (synthesizer/simulator limitation, management decision, etc.), the parser should flag any syntax that is not 1993 compliant. This should include flagging syntax that is 2008 compliant but not 1993 compliant. In other words, we need to strictly enforce a particular version and not mix versions within a VHDL file.

Ideally, it would make sense to be able to select the language version for each file in a project, and perhaps have a default version for the project that would be applied to new files. This would allow the use (and syntax enforcement) of VHDL-1993 files and VHDL-2008 files within the same project. This makes sense as new files targeting VHDL-2008 will likely need to coexist with existing files that were written for VHDL-1993. This is also consistent with how Xilinx identifies a file type property for each file in their Vivado toolset.

I have no appreciation for how difficult this would be as I have no experience with Eclipse plugins or javacc. So the required effort may be unreasonable for this project. However, without the user being able to select the version, I suggest that VHDL-2008 support be maintained in a separate branch. That way we can choose a 1993 or a 2008 version of the plugin without muddling the two.

Thoughts?

[ssharks]

Dear btrotter,

It took me a while to think about a good solution for your problem. In theory it is possible to create two different parsers for VHDL-2008 and VHDL-93, since there is a separate parser for VHDL and a separate one for Verilog.

I'm not familiar with VHDL-2008, but I think it is just an addition to VHDL-93. If there are no / not too much valid VHDL-93 statements, that are part of the VHDL 2008 syntax, you could also use the VHDL 2008 parser and make it optional to create semantic errors on VHDL-2008 specific constructions, or even on selections from VHDL-2008. This way the parser still runs successful and can find all objects, so your auto completion works, but you only semantic errors on the VHDL-2008 statements you use.

One of the problems I run into with a specific old project is that the parser supports VHDL-AMS. In this version "noise" is a keyword, but in VHDL-93 you can use it as a valid port / signal name. This way the parser marks an error where it is a valid VHDL-93 construction. This kind of issues make the semantic error approach less attractive.

I'm interested in your view on the problem. Since I don't use VHDL-2008, this is not an issue to me. If you really like to have this in Veditor, I need your help.