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sstsimulator / sst-elements

SST Architectural Simulation Components and Libraries
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Memory Hierarchy After the Simulation #2278

Open dmukherj09 opened 9 months ago

dmukherj09 commented 9 months ago

Whenever I connect any type of memory system (CramSim/DramSim3/SimpleMem) with a setup of cache hierarchy which is driven by either some generic test-cpu/prospero-trace-based/ariel-binary-based, after the simulation is complete, I don't see all the remaining data in cahe being flushe back to the main memory model.

Even during the simulation, I don't see any WRITE operation at the main memory, which is okay logically as when any WRITE is required and if the data is not in the cache hierarchy, it is first READ from the main memory and then gets written to in the cache, but that should be followed up with all the remaining final data in all the cache hierarchies to be flushed to the main memory.

Am I doing something wrong or is it intended purpose?

hughes-c commented 9 months ago

There is no cache flush at the end of the simulation. I believe that @gvoskuilen was working on something to enable that but right now, you can only flush a single cache line. So, in the epilogue, you would need to flush each individual cache line to make it visible at the end of the simulation.

dmukherj09 commented 9 months ago

Hi @hughes-c, thanks for the reply. Can you help me to figure out how to flush the cache lines one by one for now?