Ariel Core CPU cannot connect to Shared Type elements

[dmukherj09]

Hello,

I'm trying to configure a system which has a 8 core Ariel CPU connected with a shared cache which is then connected to the memory.

Since the Cache is shared, I'm using a bus -- one side 8 ports high_network_0 to high_network_7 is connected to the Ariel CPU's cache_link_0 to cache_link_7 and on the other side low_network_0 of the bus is connected to the shared cache's high_network_0.

On trying to simulate this simple setup, I get the error -- "Bus attempting to map node that has already been mapped".

How to proceed?

[gvoskuilen]

This is side-effect of memHierarchy using component names to identify event senders. To fix, you'll need to use a shim that ensures L1 requests/responses keep their core IDs since they're all coming from a single ariel component and getting sent to the same cache. The shim is called "memHierarchy.multithreadL1" and can be used instead of the bus between the cores & the cache. Something along these lines:

ariel = sst.Component(...)
cache = sst.Component(...)
shim = sst.Component("cores_to_cache", "memHierarchy.multithreadL1")
shim.addParams( ... ) # Set clock and number of requests/responses that can be handled each cycle
for x in range(0, cores):
    link = sst.Link("link_core_" + str(x))
    link.connect( (ariel, "cache_link_" + str(x), latency), (shim, "thread" + str(x), latency) )
cachelink = sst.Link("link_cache")
cachelink.connect( (shim, "cache", latency), (cache, "high_network_0", latency) )

If it's helpful, the memHierarchy test "tests/testKingsley.py" uses the multithreadL1 to connect two cores per first level cache.

[jwilso]

Closing as resolved.