Feature: [Running on an actual boards?]

[liubenyuan]

Feature Request Summary

I request to:

• [ ] I have an adm-pcie-9v3 and an RFSOC boards with two QSFP cages, could I test this 10Gbe on an actual board?
• [ ] Is there any external chips, or IPs from xilinx or altera required?

Feature Details

We would like to test this on either ADM-PCIE-9V3 or an ultrascale+ FPGA.

Purpose, Expected Benefit

It would improve the usability of this repository.

[staerz]

Hi @liubenyuan,

thanks for your request.

Yes, with a little bit of embedding work, you should be able to test the core for your board.

What you'll need to do is to interconnect the Ethernet interface of the core provided with the high level interface of your network adapter to connect it to the low level interface. This is usually done via dedicated IP cores (from Intel or Xilinx, depending your particular board / FPGA on it). In particular, we're talking about the MAC (Media access layer) which is not part of this XGbE_lib repo.

So what the XGbE_lib does is to provide UDP interfaces (ports) to the user and take care of the wrapping in proper Ethernet frames (and all the ARP/ICMP/DHCP management associated).

I hope that answers your questions.

[liubenyuan]

Thank you! I will try to run your project first, may be simulation of synthesis using vivado.

BTW, is the logic of this project compatible with 100G CMAC for ultrascale+?

[staerz]

Hi @liubenyuan,

XGbE_lib uses an 8 byte per clock cycle interface which is intended to be run at 156.25 MHz to make it 10 GbE. That usually is also (or at least used to be at some point) the interface of the provided 10G MACs of Intel (or Altera at that point).

From that you should understand that it won't be directly compatible with a 100G MAC.

If you're willing to compromise on throughput I could imagine that you write your own adapter module to convert the interface of XGbE_lib to the 100G MAC. The rx_fifo_module might be a template that you could get inspiration from: I recommend to buffer each packet in a FIFO in order to be able to provide a continuous stream of data and to get the eof indicator correct - in both directions.

It would be up to you to find out the maximum frequency that can be achieved for the implementation of XGbE_lib (you can, of course, always overclock it to not suffer from a 1:10 decrease in throughput, but maybe only 1:5 or so).

BTW: Looking at it and you mentioning Xilinx, please make sure to hook the core up with an actual FIFO for Xilinx :wink: - see the src/memory directory, esp. the xilinx_fifo.vhd.

We have demonstrated that general concept in a 1 GbE implementation where we clocked XGbE_lib with 125 MHz (which is not part of this repo) .