Open dkoeplin opened 6 years ago
I made some changes to the list with priority (smaller means more important). You can check off tasks when they are in develop. Thanks!
2 - Need to discuss with Matt - may change FPGA correctness 3 - Will be added with overhaul to banked accesses 7 - Requires representation of one-hot mux for Plasticine (or some other agreed upon thing)
2 - Seems like it won't change correctness, but it sounds more expensive maybe. The plan is to get rid of the enables that come into controllers and instead wrap them inside switches?
Can 7 be converted to nested muxes? For example
If (c1) b1 else if (c2) b2 else b3 can be converted to Mux (c1, b1, mux(c2, b2, b3))
We can add one hot mux but ALUs have max 3 operands. so won't be albe to support selection more than two inputs
@mattfel1 yeah that's the general idea. Plasticine doesn't support enables on reads/writes/etc., so it always needs explicit enabling controllers around these things.
@yaqiz01 yeah you're right I think that should work.
@dkoeplin For 1 is it possible to set Switch around the Switch Cases to have OuterControl ControlLevel? The only thing that's InnerControl level are the inner most switch cases
The following compiler changes should take effect when PIR gen is enabled: