URAMs are 72 bits wide, which means that 2 32-bit words can fit in each entry (or 4 16-bit words, etc.) This can be done in the case of sequential reads/writes, and would increase usable on-chip SRAM. The URAMs have 2 read and 2 write ports.
This can also be done for block rams on the F1 and the Zynq. It may also be easier to do for block rams because they are 32 bits wide but support multiple data widths (e.g. 1, 2, 4, 8, 16, 32) and also support acting as two indepenent block rams. BRAMs also have 2 read and 2 write ports. You can see Table 2-1 here for more information:
https://www.xilinx.com/support/documentation/user_guides/ug573-ultrascale-memory-resources.pdf
URAMs are 72 bits wide, which means that 2 32-bit words can fit in each entry (or 4 16-bit words, etc.) This can be done in the case of sequential reads/writes, and would increase usable on-chip SRAM. The URAMs have 2 read and 2 write ports.
This can also be done for block rams on the F1 and the Zynq. It may also be easier to do for block rams because they are 32 bits wide but support multiple data widths (e.g. 1, 2, 4, 8, 16, 32) and also support acting as two indepenent block rams. BRAMs also have 2 read and 2 write ports. You can see Table 2-1 here for more information: https://www.xilinx.com/support/documentation/user_guides/ug573-ultrascale-memory-resources.pdf