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stanford-ppl / spatial-lang

Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
MIT License
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Use MACC IP #232

Open shadjis opened 7 years ago

shadjis commented 7 years ago

Rather than use separate DSP blocks for multiplies and then adds, the Xilinx MACC IP can be used. This would reduce DSP utilization.

mattfel1 commented 7 years ago

So should we have a MAC analysis that checks for a multiply map function and addition reduce function?

dkoeplin commented 7 years ago

If I understand the operation of the DSP correctly, the term MACC is actually a bit of a misnomer? It's actually just a fused multiply-add, no accumulate, meaning we just look for that pattern regardless of reduction. Maybe we prioritize reductions though?

shadjis commented 7 years ago

I think there are 2 versions,

Multiply-Add does AB + C (3 inputs) https://www.xilinx.com/products/intellectual-property/multiply_adder.html

Multiply-Accumulate does AB + previous product (2 inputs) https://www.xilinx.com/products/intellectual-property/multiply_accumulator.html

As we discussed this might not reduce DSP utilization, only logic utilization because rather than use adders inside CLBs it would use adders in DSP blocks. It might still be an important logic optimization in the future if a design has a lot of multiply-add operations but maybe it is lower priority.