Fringe Command Fifo Filling Glitch

[mattfel1]

This definitely happens in tpchq6 with outerpar = 2 and Fringe fifo depth = 16. Possibly also happens in gda, lenet, and sobel when running on the board.

Quick fix is to add random backoff to each dram transaction in codegen. Awaiting long-term solution.

[mattfel1]

This temp fix is screwing up unaligned loads occasionally because this structure has a stream inner pipe that pushes to both the cmd stream and the fifo in the accel. If the hack delay is 1, then it is possible for the controller to push to the fifo, filling it up, and then the next cycle it would try to push to the stream but because the fifo is full, this cmd.valid true will hold until the fifo starts to drain, meaning we spam lots of commands to the cmd stream. I think the fix is either to halt retime reg chains based on their ultimate destination rather than &ing all of the ready signals, or just not having this hack. So I am getting rid of it for now.