VCS Issue with 1D DRAMs allocated after 4D DRAM

[mattfel1]

I see the correct data getting memcpyed to the correct addresses and the ranges do not overlap, but inside the accel it somehow loads garbage data that doesn't exist anywhere (16, 0, 0, 0, 16, 0 0 0, 16, ...)

    val Ds = List[scala.Int](3,16,32,64,96,128,128,128,128,128,128,0,0,0,0,0)
    val strides_dram = DRAM[Int](16)
    val col_info_dram = DRAM[Int](16)
    val row_info_dram = DRAM[Int](16)
    val Ds_dram = DRAM[Int](Ds.length)
    val layer_data = DRAM[T](LAYERS,Ds.max,ROWS,COLS)

The above works, but once the 16 element DRAMs go below layer_data, it doesn't work...

[mattfel1]

Nevermind, I had a DRAM allocation down below this where I setMem with something 10x bigger than the DRAM's size so it was washing out the other DRAMs