Closed mattfel1 closed 6 years ago
Yeah ideally we should support this kind of thing. That'll ultimately make it easier to figure out where Accel should go when we work on work distribution/allocation.
Agreed that we need this. I think fundamentally we don't have a distinction between a board-level reset (which wipes out the configuration) and a memory-mapped "design reset" that restores state elements to a clean state before Accel.
Done. Codegen just didn't enter the RangeForeach node
Should this kind of thing be supported? Right now, at least in vcs, something gets messed up in the generated accel. On the board, I don't think it will work today either because we aren't controlling the reset signal from sw and we reprogram the fpga only at the top of
main
.I don't think it would be unusual for someone with a relatively complicated app to want to do some CPU stuff between iterations of the accel. It just seems like we need to do a little busywork to get it working