generating hdl/design_1.v error while making zynq

[ShaopengChen]

I write a simple test code with target zynq, and successfully make synth, when I go to gen/test dictionary and make zynq, it runs successfully into time vivado stage, and shows errors below:

time vivado -mode batch -source bdproject.tcl -tclargs 125 2>&1 | tee vivado_bdproject.log

** Vivado v2018.1 (64-bit) SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source bdproject.tcl # if { $argc != 1 } { # puts $argc ...... VHDL Output written to : /home/shaopeng/workspace/spatial-lang/gen/HelloTest/verilog-zynq/bd_project/bd_project.srcs/sources_1/bd/design_1/sim/design_1.v VHDL Output written to : /home/shaopeng/workspace/spatial-lang/gen/HelloTest/verilog-zynq/bd_project/bd_project.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v # add_files -norecurse ./bd_project/bd_project.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v # update_compile_order -fileset sources_1 set_property top design_1_wrapper [current_fileset] # update_compile_order -fileset sources_1 # file copy -force ./bd_project/bd_project.srcs/sources_1/bd/design_1/hdl/design_1.v ./design_1.v error copying "./bd_project/bd_project.srcs/sources_1/bd/design_1/hdl/design_1.v": no such file or directory while executing "file copy -force ./bd_project/bd_project.srcs/sources_1/bd/design_1/hdl/design_1.v ./design_1.v" (file "bdproject.tcl" line 722) INFO: [Common 17-206] Exiting Vivado at Wed Aug 22 10:15:54 2018... Command exited with non-zero status 1 39.27user 4.51system 1:05.42elapsed 66%CPU (0avgtext+0avgdata 809476maxresident)k 774592inputs+18376outputs (2435major+469087minor)pagefaults 0swaps sed -i 's/design_1_Top_0_0/Top/' design_1.v sed: can't read design_1.v: No such file or directory Makefile:24: recipe for target 'bd' failed make[1]: [bd] Error 2 make[1]: Leaving directory '/home/shaopeng/workspace/spatial-lang/gen/HelloTest/verilog-zynq' Makefile:250: recipe for target 'zynq-hw' failed make: [zynq-hw] Error 2

Is there anything wrong with the generated file bdproject.tcl ? Why can hdl/design_1.v not be generated?

[ShaopengChen]

When I change Vivado version from 2018.1 to 2017.1, the issue is fixed and run make zynq successfully.

[raghup17]

Closing this issue. We can create a separate issue to track supporting Vivado 2018.1.