PipeInsertion Inside of Stream Controller Not Respecting Stream Scheduling

[mattfel1]

Exposed in MergeSort

doubleBuf is a Reg that is correctly written outside of the stream controller. However, the else condition's reg is written inside of the stream controller in a unit pipe placed at the very front, so both doubleBuf and the inserted Reg can be true at the moment when the Switch executes

      Sequential.Foreach(0 until levelCount) { level =>
          Stream {
            ...
            if (doubleBuf) {
              memBuffer(sAddr) store mergeBuf
            } else {
              mem(sAddr) store mergeBuf
            }
          }
        }
        Pipe {
          doubleBuf := !doubleBuf
        }
      }

[mattfel1]

Root cause was PipeInserter wrapping the Not(cond) in a unit pipe as a write to a reg, and then reading the reg right before the switch. I added some FIFOReg nodes (name should probably change to something more descriptive) which are just registers that have a status flag that can be used for register communication between stages in stream controllers. It will insert one of these registers if the parent is a Stream.