Frustrating Systolish Behavior

[mattfel1]

I thought there was an old issue about this but I can't find it now and I forgot what we decided. Here's what I think makes sense now though, because this has tripped up a few of us a few times now and is very unpleasant to debug since it looks good from a software perspective and runs as expected in --sim but not in --synth.

Pipe{
  reg := b
  ... = reg
}

and

Pipe{
  ... = reg
  reg := b
}

Retiming treats both cases the same since there is no cycle detected between the two, and in both cases the ... takes on whatever value is in reg before we write b into it.

In the fullDFS, I'm going to add extra deps to writers if they read from a memory and a write to that memory occurs in the same scope but earlier. schedule is a Seq so I think it will preserve program order.

[mattfel1]

From a user point of view, I think this is similar to the common mistake of declaring a register with an initial value inside a loop and expecting it to reset the register on each iteration of the loop. I think --sim and --synth are at least consistent for this one though so the issue above though is probably more frustrating to debug