StreamIn not banked

[yaqiz01]

This app doesn't run for fpga backend since FileBus is something I recently added. But I'm expecting StreamIn in to be banked by 4. Right now is banked by 1.

import spatial.dsl._                                                                                                                                                                 
import spatial.lang.{FileBus,FileBusLastBit}                                                                                                                                         

@spatial class StreamInOut extends DSETest {                                                                                                                                         
  val inFile = "in.csv"                                                                                                                                                              
  val outFile = "out.csv"                                                                                                                                                            
  val numToken = 16                                                                                                                                                                  
  def main(args: Array[String]): Unit = {                                                                                                                                            
    val inData = Matrix.tabulate(numToken,2) { (i,j) =>                                                                                                                              
      if (j == 0) random[Int](10) else random[Int](2)                                                                                                                                
    }                                                                                                                                                                                
    writeCSV2D(inData, inFile)                                                                                                                                                       
    val in  = StreamIn[Tup2[Int,Bit]](FileBus[Tup2[Int,Bit]](inFile))                                                                                                                
    val out = StreamOut[Tup2[Int,Bit]](FileBus[Tup2[Int,Bit]](outFile))                                                                                                              
    Accel(*){                                                                                                                                                                        
      Foreach(4 by 1 par 4) { i =>                                                                                                                                                   
        out := in.value                                                                                                                                                              
      }                                                                                                                                                                              
    }                                                                                                                                                                                
    val outData = loadCSV2D[Int](outFile)                                                                                                                                            
    val cksum = inData == outData                                                                                                                                                    
    println("PASS: " + cksum + " (StreamInOut)")                                                                                                                                     
    assert(cksum)                                                                                                                                                                    
  }                                                                                                                                                                                  
}  

[mattfel1]

fixed