MergeBuffer Banking

[yaqiz01]

This app crashes on banking for the merge buffer if I attempt to pipeline read and write accesses of the mergeBuf. MergeBuffer have ways number of inputs and bounds. enq(way, data) and bound(way, b) are actually writing to independent vectorized input streams internally. I just want the app to pass the memory configuerer with 1 instance of mergebuffer.

@spatial class MergeBufferTest extends SpatialTest {                                                                                                                                                                                                                          
  type T = Int                                                                                                                                                                                                                                                                

  val N = 64                                                                                                                                                                                                                                                                  
  val ip = 16                                                                                                                                                                                                                                                                 
  val op = 1                                                                                                                                                                                                                                                                  

  def main(args: Array[String]): Unit = {                                                                                                                                                                                                                                     
    val dram = DRAM[T](N)                                                                                                                                                                                                                                                     

    val nway = 2                                                                                                                                                                                                                                                              
    val ways = scala.List.tabulate(nway) { i => i }                                                                                                                                                                                                                           

    val bs = nway * ip                                                                                                                                                                                                                                                        

    Accel {                                                                                                                                                                                                                                                                   
      val mergeSize = ip                                                                                                                                                                                                                                                      
      Foreach(N by bs par op) { i =>  // Works if this is Sequential                                                                                                                                                                                                                                         
        val mergeBuf = MergeBuffer[T](nway, ip)                                                                                                                                                                                                                               
        val insram = SRAM[T](bs) // Initially in reverse order                                                                                                                                                                                                                
        Foreach(0 until bs) { j =>                                                                                                                                                                                                                                            
          insram(j) = bs - 1 - j                                                                                                                                                                                                                                              
        }                                                                                                                                                                                                                                                                     
        mergeBuf.init(true)                                                                                                                                                                                                                                                   
        ways.foreach { w =>                                                                                                                                                                                                                                                   
          mergeBuf.bound(w, mergeSize)                                                                                                                                                                                                                                        
          Foreach(0 until mergeSize par ip) { j =>                                                                                                                                                                                                                            
            mergeBuf.enq(w, insram(mergeSize*w + j))                                                                                                                                                                                                                          
          }                                                                                                                                                                                                                                                                   
        }                                                                                                                                                                                                                                                                     
        val fifo = FIFO[T](bs)                                                                                                                                                                                                                                                
        Foreach(0 until bs par ip) { j =>                                                                                                                                                                                                                                     
          fifo.enq(mergeBuf.deq())                                                                                                                                                                                                                                            
        }                                                                                                                                                                                                                                                                     
        dram(i::i+bs par ip) store fifo                                                                                                                                                                                                                                       
      }                                                                                                                                                                                                                                                                       
    }                                                                                                                                                                                                                                                                         

    assert(true)                                                                                                                                                                                                                                                              
  }                                                                                                                                                                                                                                                                           
}

[mattfel1]

Switched MergeBuffer to use the custombanked analyzer since that is a thing that exists now.