Expose Stream to Frame explicitly

[mattfel1]

Right now, the StreamIn/Out is implicitly created with the FrameIn/Out. I think it would be better to have this kind of syntax so we can have one less controller for this kind of situation:

Current:

    val in = FrameIn[U32](64)  // Sends data over AxiStream256Bus, but only lowest 32 bits have real data
    val data = Array.tabulate[U32](64){i => i.to[U32]}
    setFrame(in, data)
    Accel {
      Stream {
        val a = FIFO[U32](8)
        a load in
        // use a
        ...
      }
    }

Proposed:

    val inbus = StreamIn[AxiStream256](AxiStream256Bus(id=0, dest=0)) // Corresponds to localhost port 8002 in rogue-land, see https://github.com/slaclab/axi-pcie-core/blob/pre-release/shared/rtl/AxiPcieDma.vhd#L311-L324)
    val data = Array.tabulate[U32](64){i => i.to[U32]} // Could be a txt file too
    val in = Frame[U32](size=data.length, inbus) // Only lowest 32 bits on TDATA contain data.  
    setFrame(in, data)
    Accel {
      Stream {
        // use inbus.tdata directly, no need for intermediate FIFO or lowering rule for "a load in" that creates a 64-iteration cchain
       // Since inbus is type AxiStream256, you technically have access to tdata, tdest, tid, tuser, etc. in the app since AxiStream256 is a @struct
        ...
      }
    }

Frame is a non-directioned software container for one-time-transmit data to or from the accel

[mattfel1]

Done