Give User Some Control Over Retiming

[mattfel1]

For example, a user (me) may write something like

Foreach(N by 1){ i => 
    val addr = i % 15 // Long operation
    mem(addr) = i
    val rd = mem(i)
}

Retiming will schedule the read before the write. But I want some way to indicate that I don't want the read to get scheduled until at least after the write has happened. My blunt weapon of choice for handling this would be:

Foreach(N by 1){ i => 
    val addr = i % 15 // Long operation
    mem(addr) = i
    // Stuff 1
    retimeGate()
    val rd = mem(i)
    // Stuff 2
}

The retime analyzer would retime as normal, and then push everything in program order after retimeGate just enough so that the earliest node in Stuff 2 happens at least 1 cycle after the latest node in Stuff 1. I think a user who uses this is playing with fire, but as of now the only way to do what I need is to add some dummy logic that I know will put them in the order I want.

[mattfel1]

Also want to add syntax like:

val x = retime(y, 3)

to automatically put retime registers there for me. This is also something that an ordinary user should never use, but will help me with using Spatial to generate controller subtrees that I want to rip out and synthesize out-of-context. This syntax may take slightly more than one step to add, since I don't think the retime modeling right now will be happy with DelayLine nodes that it didn't put there itself.

[mattfel1]

:tada: