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stanford-ppl / spatial

Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
https://spatial.stanford.edu
MIT License
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Fancy Blackbox Support #287

Closed mattfel1 closed 4 years ago

mattfel1 commented 4 years ago

I just implemented Verilog blackboxes. They assume the IP has implicit clock and reset ports, and then the user specifies the rest of the interface and it works. The user specifies an input @struct, output @struct, verilog file path, bbox latency, and whether the bbox is pipelined (II constraint = 1).

By "fancy," I mean the following interrelated things. My plan is to not worry about them until we have real use-cases. I think 4 will be the next thing to solve, but it kind of needs 1-3 to be solved first:

  1. How to nicely handle blackboxes with enables? Obviously they would wire to the controller's datapath enable but what should the syntax in Spatial be?
  2. How to handle bboxes that have dynamic latency, and where would these fit in with the inner/outer hierarchy?
  3. How to handle bboxes with ready/valid interfaces? What is the syntax and how do they fit in the hierarchy?
  4. How to handle Spatial blackboxes? Syntax and compiler modifications so that programmer can make one hardware unit and then copy/paste it throughout the app so that we only need to run retiming/analysis/transformers once for the module. Maybe long term this can be how we handle quick unrolling, but there could be tiny details that would make this not work.
mattfel1 commented 4 years ago

Done. See Blackboxes.scala for all kinds of usage examples.