ClockSP 5 reports running slow by about 2%

[SteveFosdick]

A new version of ClockSP was released. Discussion at: https://stardot.org.uk/forums/viewtopic.php?p=379781#p379781

Running on B-Em both BBC and BBC Master with BASIC IV (MOS 3.2) report runing slow by about 2%, i.e. report running at c. 1.98Mhz rather than 2Mhz.

ClockSp 5 on B-Em Emulating the BBC B The 6502 Timing Tester running on B-Em Emulating a BBC B ClockSp 5 on B-Em Emulating the BBC Master The 65C122 Timing Tester running on B-Em Emulating a BBC Master

[SteveFosdick]

The largest part of this issue turns out to be the OS spending time on serial code if the transmit data register entry status is asserted even if this was not the cause of the interrupt, i.e. this is also checked again from the 100Hz timer interrupt. See https://stardot.org.uk/forums/viewtopic.php?p=379933#p379933

With TDRE bodged to false the result is much closer:

[SteveFosdick]

Issue of ACIA TX ready status solved in https://github.com/stardot/b-em/commit/db54afa7e6408fb24f15abb810bb0f1b7c1f4cc8. Ability to capture serial output restored in https://github.com/stardot/b-em/commit/e31bf8fbc028e3542aa3460e6d885398d6d52f65