Should be possible to build with a RISC-V Linux toolchain

[tpetazzoni]

Right now, building the ddrinit code requires using the bare-metal toolchain provided from Sifive, it references a nano.spec gcc spec file that is apparently only available in the Sifive bare-metal toolchain. It should however be possible to build the ddrinit code with a regular Linux toolchain for RISC-V. This will make life much simpler for build systems such as Yocto/Buildroot. Both OpenSBI and U-Boot, while being bare-metal code, build perfectly fine with a Linux toolchain.

[davidlt]

nano.spec comes from newlib-nano, which might be available as a package in Debian at least.

See discussion here: https://github.com/starfive-tech/beagle_secondBoot/issues/3

[sndwvs]

for ddrinit the flags are slightly different

--- a/build/Makefile    2021-12-16 17:37:22.457037194 +0200
+++ b/build/Makefile    2021-12-16 17:48:42.878889216 +0200
@@ -2,11 +2,11 @@
 # Copyright (c) 2020 StarFiveTech, Inc

 # compiler tool chain
-CROSSCOMPILE?=riscv64-unknown-elf-
-CC=${CROSSCOMPILE}gcc
-LD=${CROSSCOMPILE}ld
-OBJCOPY=${CROSSCOMPILE}objcopy
-OBJDUMP=${CROSSCOMPILE}objdump
+CROSS_COMPILE?=riscv64-unknown-elf-
+CC=${CROSS_COMPILE}gcc
+LD=${CROSS_COMPILE}ld
+OBJCOPY=${CROSS_COMPILE}objcopy
+OBJDUMP=${CROSS_COMPILE}objdump

 # SoC IS JH7100 FOR VISIONFIVE OR BEAGLEV OR EVBV1 
 SoC=JH7100
@@ -35,10 +35,11 @@
 CFLAGS += -march=$(RISCV_ARCH)
 CFLAGS += -mabi=$(RISCV_ABI)
 CFLAGS += -mcmodel=medany
+CFLAGS += -ffreestanding
 CFLAGS += $(INCLUDE_DIR)
 CCASFLAGS= -mcmodel=medany -mexplicit-relocs   

-LDFLAGS = -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)-T $(LINKER_SCRIPT) -nostartfiles --specs=nano.specs -Wl,-Map,$(MAP_FILE)
+LDFLAGS = -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)-T $(LINKER_SCRIPT) -nostartfiles -lgcc -Wl,-Map,$(MAP_FILE),--build-id=none

 # object list
 OBJECTLIST=../boot/start.o\

[orangecms]

Hi, I'm rewriting this here in Rust for oreboot, which can then just be built with the default Rust toolchain. There is a lot of unnecessary code in this repo that is not about DRAM, e.g., SDIO and GPT. I will only translate the many magic values written to the many registers.

[orangecms]

Just FYI: The rewrite works fine. I've been using it all along; pending in this PR: https://github.com/oreboot/oreboot/pull/606

With the JH7100 no longer produced (as it seems?), it may sound a bit odd to have gone through the effort. However, it turns out that the successor JH7110 has the same DRAM controller and PHY, just with some slightly different parameters, so we're working on that now, porting it over from StarFive's U-Boot code. Ours is orders of magnitude smaller and more efficient (only 25% binary size!). We will have SBI included in a single stage and hand over to LinuxBoot directly. Some minor issue remains though, likely with clocks. Otherwise, we're quite done: https://github.com/oreboot/oreboot/pull/686 You're welcome to join the effort!