Known issue: L2 cache flushing due to StarFive 7100 architecture

[pdp7]

The BeagleV beta boards have the StarFive 7100 SoC which was from a limited multi-project wafer (MPW) run. StarFive is working on an improved SoC called the 7110. This will have 4x SiFive U74 cores as well as Imagination GPU and PCIe controller.

There are two known issues related to L2 cache in the 7100 SoC:

• L2 cache controller has a bug where it incorrectly raises the L2 DirFail interrupt. The only work around for this is to mask the L2 cache interrupt on the PLIC.
• All the peripherals in the 7100 are on a non-coherent bus. This requires the drivers to flush L2 cache in many instances where it is not necessary on other SoC’s. This design choice reduces the performance of the 7100.

StarFive has resolved the L2 cache controller DirFail interrupt bug in the 7110. And more importantly they have improved the SoC architecture. High performance peripherals like the Gigabit Ethernet and USB3 controller will be connected to a cache-coherent bus.

[pdp7]

Note on JH7100 Cache Coherence has been published https://github.com/starfive-tech/beaglev_doc/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf

[yimingyiming]

Sorry for this SOC design issue. The issue had nothing to do with CPU U74.

We found L2 cache problem in GMAC driver at first. GMAC have it’s own DMAC which transfer data between DDR and FIFO buffer of GMAC with tx/rx descriptors. The L2 cache coherency problem was CPU can see old data in L2 cache. But CPU cannot SEE the newer data transfered by GMAC DMAC in RX a new frame.

There are no cache coherency problem between HARTs in SoC.

The idea using the uncacheable DDR alias(0x10_0000_0000 - 0x17_FFFF_FFFF) was our initial idea. We have implemented it in uboot and found performance was poor than the flush cache solution. The flush cache solution in 7100 is a work-around solution temporarily.

I think that the idea CMA/dma_pool + uncacheable alias for the peripherals maybe effect other usage of dma_pool.

The “fence” in starfive_flush_dcache cannot omit and cannot do only one fence at the end. It would produce cache data confusion and we have tried it last year.

Because GMAC have it’s own DMAC, I think that SGDMA2P can do nothing in this case.