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starksbe
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ISU-ECE-5508-S23
Idaho State University repository for FPGA projects in ECE5508 (Advanced Digital Logic Design) spring 2023.
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37 develop crc implementation for basys3 board
#39
starksbe
closed
1 year ago
0
docs for final report and documentation of CRC
#38
Roomybear
closed
1 year ago
0
Develop CRC Implementation for Basys3 Board
#37
starksbe
closed
1 year ago
0
35 develop final changes for simulation presentation
#36
starksbe
closed
1 year ago
1
Develop Final Changes for Simulation Presentation
#35
starksbe
closed
1 year ago
0
27 develop systemverilog crc 8 decoder module
#34
starksbe
closed
1 year ago
1
Document Design of SystemVerilog CRC-8 Encoder Module
#33
starksbe
closed
1 year ago
0
Document Design of SystemVerilog CRC-8 Decoder Module
#32
starksbe
closed
1 year ago
0
26 develop systemverilog crc 8 encoder module
#31
starksbe
closed
1 year ago
0
Updated to 8-bit CRC. All that needed to change were names and some n…
#30
Roomybear
closed
1 year ago
0
Change CRC-16 Decoder to CRC-8 Decoder in Python
#29
starksbe
closed
1 year ago
1
Change CRC-16 Encoder to CRC-8 Encoder in Python
#28
starksbe
closed
1 year ago
1
Develop SystemVerilog CRC-8 Decoder Module
#27
starksbe
closed
1 year ago
1
Develop SystemVerilog CRC-8 Encoder Module
#26
starksbe
closed
1 year ago
1
Create Standard I/O Test for CRC-8 Decoder
#25
starksbe
closed
1 year ago
0
Create Standard I/O Test for CRC-8 Encoder
#24
starksbe
closed
1 year ago
0
Initialized SystemVerilog Project Structure
#23
starksbe
closed
1 year ago
2
Initialize SystemVerilog Project Directories
#22
starksbe
closed
1 year ago
0
Resolved Issues with CRC Encoder/Decoder and Built Test Functions
#21
starksbe
closed
1 year ago
1
17 create simulation with prints to show crc working presentation for dr k
#20
Roomybear
closed
1 year ago
0
Print statements for Encoder
#19
Roomybear
closed
1 year ago
0
Debug CRC-16 Encoder and Decoder for 16-Bit CRC
#18
starksbe
closed
1 year ago
0
Create Simulation with Prints to Show CRC Working (Presentation for Dr. K)
#17
starksbe
closed
1 year ago
1
13 develop crc 16 encoder python simulation
#16
starksbe
closed
1 year ago
0
Created CRC-16 Decoder Algorithm
#15
starksbe
closed
1 year ago
2
Develop CRC-16 Decoder Python Simulation
#14
starksbe
closed
1 year ago
1
Develop CRC-16 Encoder Python Simulation
#13
starksbe
closed
1 year ago
1
6 bes build repository structure for project
#12
starksbe
closed
1 year ago
0
Add System Diagram to Repository
#11
starksbe
closed
1 year ago
0
Create and Deliver Project Proposal
#10
starksbe
closed
1 year ago
1
Install Xylinx Vivado and Setup Development Environment
#9
starksbe
closed
1 year ago
0
Setup Zoom Meeting for Planning & Progress Reporting
#8
starksbe
closed
1 year ago
4
Schedule Time to View FPGA Boards
#7
starksbe
closed
1 year ago
3
Build repository structure for project.
#6
starksbe
closed
1 year ago
0
Determine FPGA project deliverable(s).
#5
starksbe
closed
1 year ago
9
Purchase selected FPGA board.
#4
starksbe
closed
1 year ago
0
Obtain funding for selected FPGA board.
#3
starksbe
closed
1 year ago
0
Complete the Contributors List
#2
starksbe
closed
1 year ago
0
Select FPGA board to use for project.
#1
starksbe
closed
1 year ago
3