This is a really nice improvement. Removing the '245s reduces component count at the small cost of lightly loading the bus a little. It also reduces latency slightly (about 8-12 ns) which ensures that even on the fastest overclocks the data will always be latched within 1 processor cycle.
Personally, I would rename /CE to /CS for each device because enabling the device is one physical pin and selecting the device is another. As it stands, the distinction is important because mild power savings and bus load reduction can be achieved by only enabling the memory chips when being accessed. At other times they will be in power saving mode and their IO pins will be Hi-Z. You could look at ganging the /CE and /CS pins on the SRAMs and seeing how the enable slows data being stable.
There's also the option of mirroring the internal DRAM that isn't used as memory mapped IO. Reads from the screen RAM are relatively slow, and can cause read-modify-write cycles to extend by two or even three clocks on a very frequent basis. Mirroring this RAM for writes and using it as shadow RAM for reads can provide a notable improvement in responsiveness during heavy screen read/write activity.
Thank you for maintaining this and for taking on board my previous suggestions.
This is a really nice improvement. Removing the '245s reduces component count at the small cost of lightly loading the bus a little. It also reduces latency slightly (about 8-12 ns) which ensures that even on the fastest overclocks the data will always be latched within 1 processor cycle.
Personally, I would rename /CE to /CS for each device because enabling the device is one physical pin and selecting the device is another. As it stands, the distinction is important because mild power savings and bus load reduction can be achieved by only enabling the memory chips when being accessed. At other times they will be in power saving mode and their IO pins will be Hi-Z. You could look at ganging the /CE and /CS pins on the SRAMs and seeing how the enable slows data being stable.
There's also the option of mirroring the internal DRAM that isn't used as memory mapped IO. Reads from the screen RAM are relatively slow, and can cause read-modify-write cycles to extend by two or even three clocks on a very frequent basis. Mirroring this RAM for writes and using it as shadow RAM for reads can provide a notable improvement in responsiveness during heavy screen read/write activity.
Thank you for maintaining this and for taking on board my previous suggestions.