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stevehoover / warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
https://warp-v.org
BSD 3-Clause "New" or "Revised" License
223 stars 54 forks source link

External Memory Interface #106

Closed ALI11-2000 closed 2 years ago

ALI11-2000 commented 2 years ago

Added External Memory interfaces supporting skywater SRAM for data and instruction memory.

netlify[bot] commented 2 years ago

Deploy Preview for warp-v canceled.

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