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stevehoover / warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
https://warp-v.org
BSD 3-Clause "New" or "Revised" License
229 stars 57 forks source link

Bump riscv-formal to @03501a0 #20

Closed ahadnagy closed 4 years ago

ahadnagy commented 4 years ago

Riscv-formal updated to the newest version with the necessary modifications made in H/W.