warp-v added instruction encoding (F,A,D extension) and fpu reg file

stevehoover / warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

https://warp-v.org

BSD 3-Clause "New" or "Revised" License

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Closed vineetjain07 closed 4 years ago

vineetjain07 commented 4 years ago

1) Added remaining Instruction encoding for F,A,D- extensions 2) Added reg-file for FPU 3) Added FPU logic (currently error)

vineetjain07 commented 4 years ago

Travis successful build

vineetjain07 commented 4 years ago

Sir, any more changes needed to incorporate

vineetjain07 commented 4 years ago

changed "Todo" to "TODO" and removed \SV and /verilator ... / comments