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stevehoover / warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
https://warp-v.org
BSD 3-Clause "New" or "Revised" License
229 stars 57 forks source link

RV32IM + formal checks #36

Closed shivampotdar closed 4 years ago

shivampotdar commented 4 years ago

Enables formal checks for the RISC-V M extension with necessary changes in logic for handling long-latency instructions, M extension interface and RISC-V formal interface.

shivampotdar commented 4 years ago

Great work, both of you!!!

Thanks a lot. Kudos to @vineetjain07 for all the help :)