steveicarus / iverilog

Icarus Verilog
https://steveicarus.github.io/iverilog/
GNU General Public License v2.0
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Undetected error when a whole array is both procedurally and continuously assigned. #1090

Closed martinwhitaker closed 9 months ago

martinwhitaker commented 9 months ago

This code should be rejected:

module test();

logic [7:0] p[1:0];
logic [7:0] q[1:0];

assign q = p;

initial q = '{ 0, 0 };

endmodule

Similarly if q is connected to a module output port.

martinwhitaker commented 9 months ago

This is now fixed in the master branch.