Closed martinwhitaker closed 9 months ago
This code should be rejected:
module test(); logic [7:0] p[1:0]; logic [7:0] q[1:0]; assign q = p; initial q = '{ 0, 0 }; endmodule
Similarly if q is connected to a module output port.
q
This is now fixed in the master branch.
This code should be rejected:
Similarly if
q
is connected to a module output port.