Improve error message in module instantiation when `wire` array given to `output` array with wrong lengths

Description

I believe that the error given in the following test case is a very bad error message.

The error is that the output spec is an array with 8 elements, but the wire associated with that output is an array with 16 elements.

It would be better if the error message for this case said to check the lengths of the arrays, instead of the current error: Unpacked dimensions are not compatible in array assignment. message.

Perhaps "Unpacked array dimensions are mismatched in port definition during module instantiation.", or something like that?

Example

module test_module (
        input input_1,
        input [31:0] state_input [7:0],

        output [31:0] state_output [7:0] // Observe that this is an array with 8 elements
    );

    // do random assignment (detail not important)
    genvar i;
    generate
        for (i=0; i<8; i=i+1) begin
            assign state_output[i] = state_input[i] ^ {32{input_1}};
        end
    endgenerate
endmodule

/////////////////////////////////////////

module tb_test_module;
    reg [31:0] state_input [7:0];

    wire [31:0] state_output [15:0]; // Observe that this is an array with 16 elements

    test_module dut (
            .input_1(1'b1),
            .state_input(state_input),
            .state_output(state_output)
        );

endmodule

Error (currently):

> iverilog -g2012 -Wall error_demo.sv
error_demo.sv:27: error: Unpacked dimensions are not compatible in array assignment.
error_demo.sv:27:      : Port 3 (state_output) of test_module is connected to state_output
1 error(s) during elaboration.

steveicarus / iverilog