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steveicarus / iverilog

Icarus Verilog
https://steveicarus.github.io/iverilog/
GNU General Public License v2.0
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vvp: array.cc:1561: void compile_array_alias(char*, char*, char*): Assertion `mem' failed. #1113

Closed grebe closed 7 months ago

grebe commented 7 months ago

The following:

module __sample__main(
  input wire [48:0] x1,
  output wire [48:0] out
);
  wire [48:0] x17[0:0];
  assign x17[0] = x1;
  assign out = {x17[0]};
endmodule

triggers the following vvp error for me at ef7f0a8f38782dfc0872b1e352ccf32343c10bb8:

vvp: array.cc:1561: void compile_array_alias(char*, char*, char*): Assertion `mem' failed.