steveicarus / iverilog

Icarus Verilog
https://steveicarus.github.io/iverilog/
GNU General Public License v2.0
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Update handling of single-element arrays. #1115

Closed grebe closed 7 months ago

grebe commented 7 months ago

Also, add a test. This fixes #1113.

grebe commented 7 months ago

I'm new to the codebase and only sort-of understand what this is doing, so feel free to give feedback if I should do something else.

martinwhitaker commented 7 months ago

From vvp's point of view your fix converts the array into a single vector. This gives the correct behaviour for simulation, but does affect the VPI view of the design. I think a better fix would be

--- a/tgt-vvp/vvp_scope.c
+++ b/tgt-vvp/vvp_scope.c
@@ -697,7 +697,8 @@ static void draw_net_in_scope(ivl_signal_t sig)
                       so the word count for the signal and the alias
                       *must* match. */

-                 if (word_count == ivl_signal_array_count(nex_data->net)) {
+                 if ((ivl_signal_dimensions(nex_data->net) > 0) &&
+                      word_count == ivl_signal_array_count(nex_data->net)) {
                    if (iword == 0) {
                      fprintf(vvp_out, "v%p .array \"%s\", v%p; Alias to %s \n",
                              sig, vvp_mangle_name(ivl_signal_basename(sig)),

Note that the if (iword == 0) must be retained, otherwise the alias will be repeated for every word in the array. It's hard to demonstrate that though, as AFAICT the compiler never generates an alias for an entire array.

grebe commented 7 months ago

Ah, that makes sense. I've just pushed the fix you proposed.

martinwhitaker commented 7 months ago

Merged. Thanks for your contribution.