steveicarus / iverilog

Icarus Verilog
https://steveicarus.github.io/iverilog/
GNU General Public License v2.0
2.8k stars 520 forks source link

Access of huge 3-dimensional packed memory ignores third dimension in certain circumstances. #112

Closed vadixidav closed 8 years ago

vadixidav commented 8 years ago

Description and Links

Here is the link to the line in question. In this circumstance, this block executes due to a received interrupt. Unfortunately, although the smaller conveyor_heads packed array is updated correctly (indicating that this branch was in fact taken on the clock), the data that was supposed to be written to conveyors[1] was instead written to conveyors[0]. This is an image of the waveform in GTKWAVE. Here is an image showing the values of each conveyor with conveyors highlighted, though slightly cut off.

As can be seen from the waveform and values, the active conveyor updates appropriately, but the values are written to the wrong conveyor.

First thoughts

Supposing that it might be fixed by changing the order from big endian to little endian, I changed the conveyors order to [0:1] from [1:0]. This resulted in iverilog always writing to the [1] instead of the [0] location. By this assumption, it seems that the array indexing is occasionally ignored for packed arrays. This was true for the conveyor_heads reg as well as the conveyors reg.

Temporary solution

I changed the [1:0] to specify an unpacked array, as it was unnecessary in this case. With unpacked arrays, this issue does not happen, but it MAY happen with packed arrays without notice, though only sometimes. Here is the commit in which I fixed the issue, if anyone else encounters this and needs to fix it.

martinwhitaker commented 8 years ago

This should now be fixed in both the master and the v10 branches. Thanks for reporting this.