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steveicarus / iverilog

Icarus Verilog
https://steveicarus.github.io/iverilog/
GNU General Public License v2.0
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The simulation of iverilog and other tools is inconsistent #1132

Closed Noah-S-E closed 5 months ago

Noah-S-E commented 5 months ago

The simulation results of syn_vivado.v synthesized by Vivado using iverilog and Vivado are inconsistent

For this, I tried on edaplayground. https://www.edaplayground.com/x/Fd7p You can use Aldec Riviera Pro 2023.04 and Icarus Verilog 12.0 for separate simulations.

This is the simulation result of iverilog

101000000000000001100
101000000000000010100
101000000000000001000
101000001000000011000
101000001000000001010
101000001000000011000
101000001000000000000
101000001000000011000
101000001000000010000
101000001000000011100
101000001000000011100
101000001000000001110
101000001000000001000
101000001000000001100
101000001000000010010
101000001000000010000
101000001000000001000
101000001000000010100
101000001000000001000
101000001000000000110
101000000000000011000

Here are the simulation results of Aldec Riviera Pro 2023.04

# KERNEL: 101000000000000001100
# KERNEL: 101000000000000010100
# KERNEL: 101000000000000001000
# KERNEL: 101000000000000011000
# KERNEL: 101000000000000001010
# KERNEL: 101000000000000011000
# KERNEL: 101000000000000000000
# KERNEL: 101000000000000011000
# KERNEL: 101000000000000010000
# KERNEL: 101000000000000011100
# KERNEL: 101000000000000011100
# KERNEL: 101000000000000001110
# KERNEL: 101000000000000001000
# KERNEL: 101000000000000001100
# KERNEL: 101000000000000010010
# KERNEL: 101000001000000010000
# KERNEL: 101000001000000001000
# KERNEL: 101000001000000010100
# KERNEL: 101000001000000001000
# KERNEL: 101000001000000000110
# KERNEL: 101000000000000011000

I also used Vivado for simulation, and the following are the results

## current_wave_config
101000000000000001100
101000000000000010100
101000000000000001000
101000000000000011000
101000000000000001010
101000000000000011000
101000000000000000000
101000000000000011000
101000000000000010000
101000000000000011100
101000000000000011100
101000000000000001110
101000000000000001000
101000000000000001100
101000000000000010010
101000001000000010000
101000001000000001000
101000001000000010100
101000001000000001000
101000001000000000110
101000000000000011000
$finish called at time : 210 ps :

It can be clearly seen that the simulation of iverilog is different from the latter two

martinwhitaker commented 5 months ago

This looks to be the same as #1133. Again, if there is a race in your design, different simulators can quite legitimately produce different results.