Simulation results discrepancy

[LoSyTe]

During our synthesis process with Yosys, we generated two synthesis files using default and custom synthesis parameters. Theoretically, these two synthesis files should have identical logical functionality, and thus their functional simulation results should be consistent. However, when we used Icarus Verilog for simulation, we observed discrepancies in the final simulation results. We believe that this inconsistency is not due to the Yosys synthesis files but is instead caused by Icarus Verilog's handling of these files. We seek the community's assistance in addressing this issue.

my design file（rtl.v） as well as the optimization sequence as follows：

module top (y, clk, wire3, wire2, wire1, wire0); output wire [(32'ha23):(32'h0)] y; input wire [(1'h0):(1'h0)] clk; input wire signed [(2'h3):(1'h0)] wire3; input wire signed [(4'hc):(1'h0)] wire2; input wire [(4'hd):(1'h0)] wire1; input wire signed [(4'hc):(1'h0)] wire0; wire [(4'hb):(1'h0)] wire4; reg signed [(3'h6):(1'h0)] reg10 = (1'h0); reg [(2'h3):(1'h0)] reg32 = (1'h0); reg signed [(4'hf):(1'h0)] reg48 = (1'h0); reg signed [(5'h10):(1'h0)] reg116 = (1'h0); reg [(4'h9):(1'h0)] reg143 = (1'h0); assign y = {reg48,reg143,(1'h0)}; always @(posedge clk) begin reg48 <= ($unsigned((reg10 >> 8'haf)) ? reg32 : reg32); end
always @(posedge clk) begin reg143 = reg48 <= ($signed(reg116) | $unsigned(wire4[1:1])); end endmodule

The test script is：

yosys -p "
    read_verilog rtl.v         
    synth
    write_verilog syn_yosys.v"
iverilog -o wave_1 -y syn_yosys.v yosys_testbench.v
vvp -n wave_1 -lxt2 >> file1.txt
sed -i 's/wave_1/wave_2/g' file1.txt;
mv syn_yosys.v old_syn_yosys.v

yosys -p "
    read_verilog rtl.v         
hierarchy; proc; opt_dff -nodffe; opt_share; opt_clean; abc;
    write_verilog syn_yosys.v"
iverilog -o wave_2 -y syn_yosys.v yosys_testbench.v
vvp -n wave_2 -lxt2

However, as shown in the red box in the figure below, the simulation results are inconsistent. We look forward to your next reply.

Using Yosys' default synthesis process，the first line of output is:

Using Custom optimization sequence，the first line of output is: project.zip

[larsclausen]

In the example that you posted wire4 is not driven, which is then assigned to y and hence you see the X. So I'd say this is expected. Not sure if maybe with the different optimizations yosys drives the signals differently.

[caryr]

This seems like a synthesis bug. Have you verified the designs are actually 100% matching? Have you looked into the comment Lars made? Also the syn_yosys.v file is missing so we cannot actually test this as expected.