steveicarus / iverilog

Icarus Verilog
https://steveicarus.github.io/iverilog/
GNU General Public License v2.0
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Fix vvp cg array word aliasing #1168

Closed martinwhitaker closed 3 weeks ago

martinwhitaker commented 3 weeks ago

When multiple words in one array were connected to the same nexus as a single word array, the code generator was sometimes failing to generate all the necessary aliases. This was highly dependent on the elaboration order.

This fix should be more robust, but there are currently no tests in the test suite that cause the compiler to generate whole-array aliases, and I can't think of a way to make it do so as we don't yet support unpacked arrays in module ports, so that branch of the code is currently untested.