SystemVerilog String Queues inside classes

steveicarus / iverilog

Icarus Verilog

https://steveicarus.github.io/iverilog/

GNU General Public License v2.0

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SystemVerilog String Queues inside classes #192

Open feddischson opened 6 years ago

feddischson commented 6 years ago

Hi,

it would be greate to have the support to use string queues within classes (SystemVerilog). The following example gives sv_queue_example.sv:6: sorry: SV queues inside classes are not yet supported.

package abc;
  class x;
      string q[$];
  endclass
endpackage

module sv_queue_example;
endmodule

Icarus Verilog version 11.0 (devel) (s20150603-536-gca013857)

sschmitz86 commented 12 months ago

is there a timetable when we can expect this feature ? I 'am really looking forward to use iverilog for my tests but for me it relays on vunit support.