$random() w/ modulo bug

[Mop-u]

Unusual behavior when using modulo with $random(). changing $random()%32; to $random()%'d32; fixes the issue, but obviously this can be a source of great confusion when it comes time to debug things (as I've experienced firsthand 😅)

iverilog -g2012 RandModulo.sv (using iverilog-v11-20201123-x64 windows build from http://bleyer.org/icarus/)

Test code:

module RandModulo();
reg clk = 0;
always #10 clk <= ~clk;

reg [15:0] Random = 0;
always_ff @(posedge clk) begin
    Random <= $random()%32;
    $display("%d",Random);
    if(Random > 32) $finish();
end
endmodule

Output:

    0
    4
65505

[martinwhitaker]

This is standard Verilog behaviour:

• $random returns a signed 32-bit value
• 32 is a signed integer value
• the modulo operation and result are signed if both operands are signed
• assigning the signed result to an unsigned variable converts negative numbers to large positive numbers

'd32 is an unsigned integer value, which is why it gives a different result.