caryr
commented
3 years ago This is almost certainly not a bug in Icarus. You may want to consider what the width of the intermediate assignment results are versus what you wrote as a single line. That should give you a clue as to why you are getting an incorrect result.
jes
Background
I have ~no idea what I'm doing with Verilog, so it is highly likely that I am just wrong about this. If so, I apologise.
I am trying to design a testbench that I can execute with iverilog to test components designed in Verilog that I will eventually create using TTL chips.
I have a repo here with my test case in: https://github.com/jes/ttl-cpu
What I did
alu.vcontains an implementation of the ALU from the Nand2Tetris course, using purely combinational logic via "assign" statements. In my mind this would create a bunch of multiplexers, and an adder and an AND gate, in hardware. A change to an input (e.g. X) would cascade through the multiplexers and the adder and update the output.You can compile
alu_tb.vwith iverilog (e.g. using the Makefile) and execute the output.What I expected to happen
The
a.outprogram produced by iverilog would not output anything because the adder would work as intended.What happened
It outputs:
Implying that the adder is not working as expected.
Other information
I tried implementing the ALU on a single line, as follows:
And then the testbench works as expected. This leads me to believe that the test failure is due to the assignments not cascading the way I expect.
I'm using iverilog 11.0, downloaded from the github release.