accumulator unable to assign to unresolved wires

[kgokarn]

Hello,

I am using Icarus Verilog for simulations using cocotb testbench. The iverilog version is 11.0 stable. Running on Ubuntu 18.04LTS.

I get an error when I run the simulation on Icarus Verilog "accumulator Unable to assign to unresolved wires". The below code is synthesisable, and also compiles without any error in other compilers such as ModelSim. Please let me know if this case is not handled in Icarus Verilog. Or if there is any workaround.

Thanks in advance.

module macb( input wire clk, input wire reset, input wire next_mac_input, input wire signed [11:0] i_activation_0, . . . input wire signed [11:0] i_weight_15, output wire signed [27:0] o_output, output wire ready_out, output wire running_out );

reg [4:0] state;
reg ready;
reg running;
reg signed [27:0] accumulator;
reg signed [27:0] acti_weight;

almost_correct_adder aca(.add1_i(accumulator), .add2_i(acti_weight), .result_o(accumulator));

always @ (posedge clk) begin if (reset | next_mac_input) begin accumulator <= 0; ready <= 0; state <= 0; running <= 0; end else begin case(state) 5'b00000: begin running <= 1; acti_weight <= i_activation_0 * i_weight_0; state <= state + 1; end . . .

            5'b01111: begin
                acti_weight <= i_activation_15 * i_weight_15;
                ready <= 1;
                running <= 0;
                state <= state + 1;
            end
            5'b10000: begin
                state <= 5'b00000;
                ready <= 0;
            end
        endcase
    end
end

assign o_output = accumulator;
assign ready_out = ready;
assign running_out = running;

endmodule

[martinwhitaker]

Please also provide the code for almost_correct_adder. A cut down version will do, providing it shows the error.

[kgokarn]

Sure. the code of almost_correct_adder is a Verilog gate netlist.

Here is the code:

module almost_correct_adder ( add1_i, add2_i, result_o ); input [27:0] add1_i; input [27:0] add2_i; output [27:0] result_o; wire n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418;

xor U323 ( result_o[9], n220, n221); xor U324 ( n221, add2_i[9], add1_i[9]); xor U325 ( result_o[8], n226, n227); xor U326 ( n227, add2_i[8], add1_i[8]); xor U327 ( result_o[7], n231, n232); xor U328 ( n232, add2_i[7], add1_i[7]); xor U329 ( result_o[6], n244, n245); xor U330 ( n245, add2_i[6], add1_i[6]); xor U331 ( result_o[5], n248, n249); xor U332 ( n249, add2_i[5], add1_i[5]); xor U333 ( result_o[4], n252, n253); xor U334 ( n253, add2_i[4], add1_i[4]); xor U335 ( result_o[3], n256, n257); xor U336 ( n257, add2_i[3], add1_i[3]); xor U337 ( result_o[2], n260, n261); xor U338 ( n261, add2_i[2], add1_i[2]); xor U339 ( result_o[27], n265, n266); xor U340 ( result_o[26], n275, n276); xor U341 ( n275, add1_i[26], n213); xor U342 ( result_o[25], n280, n281); xor U343 ( n281, add2_i[25], add1_i[25]); xor U344 ( result_o[24], n295, n296); xor U345 ( result_o[23], n302, n303); xor U346 ( n303, add2_i[23], add1_i[23]); xor U347 ( result_o[22], n313, n314); xor U348 ( n314, add2_i[22], add1_i[22]); xor U349 ( result_o[21], n322, n323); xor U350 ( n323, add2_i[21], add1_i[21]); xor U351 ( result_o[20], n326, n327); xor U352 ( n327, add2_i[20], add1_i[20]); xor U355 ( result_o[19], n338, n339); xor U356 ( n339, add2_i[19], add1_i[19]); xor U357 ( result_o[18], n348, n349); xor U358 ( n349, add2_i[18], add1_i[18]); xor U359 ( result_o[17], n352, n353); xor U360 ( n353, add2_i[17], add1_i[17]); xor U361 ( result_o[16], n360, n361); xor U362 ( n361, add2_i[16], add1_i[16]); xor U363 ( result_o[15], n370, n371); xor U364 ( n371, add2_i[15], add1_i[15]); xor U365 ( result_o[14], n374, n375); xor U366 ( n375, add2_i[14], add1_i[14]); xor U367 ( result_o[13], n383, n384); xor U368 ( n384, add2_i[13], add1_i[13]); xor U369 ( result_o[12], n395, n396); xor U370 ( result_o[11], n403, n404); xor U371 ( result_o[10], n408, n409); xor U372 ( n409, add2_i[10], add1_i[10]); xor U373 ( result_o[0], add2_i[0], add1_i[0]); not U374 ( n188, n325); nor U375 ( n310, n283, n290, n319); and U376 ( n319, n187, n286); nor U377 ( n325, n321, n332); and U378 ( n332, n333, n318); nand U379 ( n333, n316, n334); nand U380 ( n334, n335, n329); and U381 ( n301, n310, n311); nand U382 ( n311, n312, n307); not U383 ( n204, n402); not U384 ( n200, n363); not U385 ( n195, n341); not U386 ( n190, n316); not U387 ( n203, n386); not U388 ( n198, n373); not U389 ( n193, n351); nor U390 ( n284, n291, n292, n293); nor U391 ( n378, n387, n388, n389); nor U392 ( n363, n359, n390); and U393 ( n390, n391, n201); nand U394 ( n391, n392, n393); or U395 ( n393, n394, n387); nor U396 ( n341, n335, n366); and U397 ( n366, n367, n330); nand U398 ( n367, n331, n368); nand U399 ( n368, n369, n364); nor U400 ( n316, n312, n344); and U401 ( n344, n345, n308); nand U402 ( n345, n309, n346); nand U403 ( n346, n347, n342); nor U404 ( n386, n382, n415); nor U405 ( n415, n413, n222); nor U406 ( n321, n215, n189); nor U407 ( n290, n214, n186); nor U408 ( n369, n219, n199); nor U409 ( n347, n217, n194); nor U410 ( n335, n218, n196); nor U411 ( n312, n216, n191); nor U412 ( n222, n377, n416); nor U413 ( n416, n228, n414); nor U414 ( n373, n369, n379); and U415 ( n379, n380, n365); nand U416 ( n380, n363, n381); nand U417 ( n381, n382, n378); nor U418 ( n351, n347, n356); and U419 ( n356, n357, n343); nand U420 ( n357, n341, n358); nand U421 ( n358, n359, n355); nand U422 ( n402, n224, n206, n205); nand U423 ( n286, n214, n186); nand U424 ( n365, n219, n199); nand U425 ( n343, n217, n194); nand U426 ( n318, n215, n189); nand U427 ( n330, n218, n196); nor U428 ( n277, n273, n279); nand U429 ( n308, n216, n191); nor U430 ( n398, n399, n400); nor U431 ( n399, n401, n389, n402); nor U432 ( n234, n236, n237); nand U433 ( n239, n407, n411); nand U434 ( n411, n241, n242, n210); not U435 ( n210, n250); nand U436 ( n400, n394, n406); or U437 ( n406, n386, n389); and U438 ( n279, n274, n285); nand U439 ( n285, n284, n286, n187); and U440 ( n235, n241, n242, n243); nand U441 ( n248, n250, n251); nand U442 ( n251, n252, n243); and U443 ( n355, n364, n330, n365); and U444 ( n329, n342, n308, n343); and U445 ( n307, n317, n286, n318); not U446 ( n211, n236); not U447 ( n205, n413); not U448 ( n206, n414); not U449 ( n202, n392); and U450 ( n283, n317, n286, n321); not U451 ( n187, n320); not U452 ( n201, n388); not U453 ( n185, n293); nand U454 ( n305, n301, n306); nand U455 ( n306, n307, n308, n192); not U456 ( n192, n309); and U457 ( n407, n401, n412); nand U458 ( n412, n209, n242); not U459 ( n209, n246); not U460 ( n207, n230); not U461 ( n197, n331); not U462 ( n184, n292); not U463 ( n208, n225); nor U464 ( n389, add2_i[10], add1_i[10]); nor U465 ( n293, add2_i[22], add1_i[22]); nor U466 ( n291, add2_i[23], add1_i[23]); nor U467 ( n387, add2_i[11], add1_i[11]); xnor U468 ( n295, add1_i[24], add2_i[24]); nor U469 ( n296, n297, n294); nor U470 ( n297, n301, n291, n293); xor U471 ( result_o[1], n417, n418); nand U472 ( n417, add1_i[0], add2_i[0]); xnor U473 ( n418, add2_i[1], add1_i[1]); nor U474 ( n292, add2_i[24], add1_i[24]); nor U475 ( n388, add2_i[12], add1_i[12]); nor U476 ( n236, add2_i[3], add1_i[3]); nor U477 ( n413, add2_i[9], add1_i[9]); nor U478 ( n237, add2_i[2], add1_i[2]); nor U479 ( n414, add2_i[8], add1_i[8]); nor U480 ( n225, n239, n240); and U481 ( n240, add1_i[3], n235, add2_i[3]); nor U482 ( n273, add2_i[25], add1_i[25]); nand U483 ( n309, add2_i[17], add1_i[17]); nand U484 ( n331, add2_i[14], add1_i[14]); or U485 ( n364, add2_i[14], add1_i[14]); or U486 ( n342, add2_i[17], add1_i[17]); or U487 ( n242, add2_i[6], add1_i[6]); nor U488 ( n267, n270, n213); nor U489 ( n270, add1_i[26], n269); or U490 ( n317, add2_i[20], add1_i[20]); or U491 ( n241, add2_i[5], add1_i[5]); or U492 ( n224, add2_i[7], add1_i[7]); xnor U493 ( n265, add2_i[27], add1_i[27]); nor U494 ( n266, n267, n268); and U495 ( n268, n269, add1_i[26]); nand U496 ( n408, n386, n410); nand U497 ( n410, n204, n239); nand U498 ( n244, n246, n247); nand U499 ( n247, n248, n241); nand U500 ( n370, n331, n372); nand U501 ( n372, n198, n364); nand U502 ( n348, n309, n350); nand U503 ( n350, n193, n342); nand U504 ( n302, n300, n304); nand U505 ( n304, n305, n185); nand U506 ( n338, n316, n340); nand U507 ( n340, n329, n195); nand U508 ( n322, n320, n324); nand U509 ( n324, n188, n317); nand U510 ( n313, n310, n315); nand U511 ( n315, n307, n190); nand U512 ( n220, n222, n223); nand U513 ( n223, n224, n206, n208); nand U514 ( n280, n279, n282); nand U515 ( n282, n283, n284); nand U516 ( n383, n363, n385); nand U517 ( n385, n378, n203); nand U518 ( n231, n207, n233); nand U519 ( n233, add2_i[1], add1_i[1], n234, n235); nand U520 ( n352, n351, n354); nand U521 ( n354, n202, n355, n201, n343); nand U522 ( n326, n325, n328); nand U523 ( n328, n197, n329, n330, n318); nand U524 ( n374, n373, n376); nand U525 ( n376, n377, n378, n205, n365); xnor U526 ( n403, add1_i[11], add2_i[11]); nor U527 ( n404, n405, n400); nor U528 ( n405, n402, n407, n389); xnor U529 ( n395, add1_i[12], add2_i[12]); nor U530 ( n396, n397, n202); nor U531 ( n397, n387, n398); nor U532 ( n276, n277, n278); and U533 ( n278, add1_i[25], add2_i[25]); nand U534 ( n230, n225, n238); nand U535 ( n238, add2_i[2], add1_i[2], n235, n211); nand U536 ( n294, n298, n299); nand U537 ( n298, add2_i[23], add1_i[23]); or U538 ( n299, n300, n291); nand U539 ( n228, add2_i[7], add1_i[7]); nand U540 ( n250, add2_i[4], add1_i[4]); nand U541 ( n246, add2_i[5], add1_i[5]); nand U542 ( n392, add2_i[11], add1_i[11]); nand U543 ( n320, add2_i[20], add1_i[20]); and U544 ( n382, add1_i[9], add2_i[9]); and U545 ( n359, add2_i[12], add1_i[12]); or U546 ( n243, add2_i[4], add1_i[4]); and U547 ( n377, add2_i[8], add1_i[8]); nand U548 ( n260, n262, n263); nand U549 ( n262, add2_i[1], add1_i[1]); nand U550 ( n263, add1_i[0], n264, add2_i[0]); or U551 ( n264, add2_i[1], add1_i[1]); nand U552 ( n256, n258, n259); nand U553 ( n258, add2_i[2], add1_i[2]); nand U554 ( n259, n260, n212); not U555 ( n212, n237); nand U556 ( n401, add2_i[6], add1_i[6]); nand U557 ( n269, n271, n272); nand U558 ( n271, add2_i[25], add1_i[25]); or U559 ( n272, n273, n274); not U560 ( n186, add1_i[21]); not U561 ( n199, add1_i[13]); not U562 ( n194, add1_i[16]); not U563 ( n196, add1_i[15]); not U564 ( n191, add1_i[18]); not U565 ( n189, add1_i[19]); nand U566 ( n394, add2_i[10], add1_i[10]); nand U567 ( n300, add2_i[22], add1_i[22]); not U568 ( n214, add2_i[21]); not U569 ( n219, add2_i[13]); not U570 ( n217, add2_i[16]); not U571 ( n218, add2_i[15]); not U572 ( n216, add2_i[18]); not U573 ( n215, add2_i[19]); nand U574 ( n360, n341, n362); nand U575 ( n362, n355, n200); not U576 ( n213, add2_i[26]); nand U577 ( n226, n228, n229); nand U578 ( n229, n230, n224); nand U579 ( n252, n254, n255); nand U580 ( n254, add2_i[3], add1_i[3]); nand U581 ( n255, n256, n211); and U582 ( n274, n287, n288, n289); nand U583 ( n289, add2_i[24], add1_i[24]); nand U584 ( n287, n294, n184); nand U585 ( n288, n290, n284); endmodule

[martinwhitaker]

A cut-down test case:

module dut(output wire result);
  assign result = 1'b1;
endmodule

module top();
  reg value;

  dut dut(value);

  initial value <= 1'b0;
endmodule

The error message you report indicates you are compiling for a SystemVerilog generation, so connecting an output port to a variable is allowed. But what isn't allowed is driving the variable from both a procedural assignment and a continuous assignment. From IEEE 1800-2012 section 6.5:

"Variables can be written by one or more procedural statements, including procedural continuous assignments. The last write determines the value. Alternatively, variables can be written by one continuous assignment or one port."

I tested this with several other Verilog compilers, and they all reported an error.

[kgokarn]

Thank you for your reply. For the accumulator, I need to have an initial value (0). Then it must be added with values from the calculation. Therefore, when the hardware is reset, the accumulator will be assigned to 0. How would you change it otherwise?

Also, is changing the accumulator from "reg" to "wire" is suggested?

If I compile it for Verilog, should it work? (I am not sure if cocotb compiles by default for SystemVerilog) I synthesised the code in Synopsys DC for Verilog and it is synthesised without an error.

Thanks in advance.

[caryr]

Maybe you want to consider that the synthesized hardware is what needs to support the reset instead of trying to implement the reset using the test/procedural code in parallel with the hardware. How would this work if you actually implemented it in hardware which is what the synthesized output is supposed to be? FYI if other simulators support this then as Martin has said they have a bug.

This is not a reg versus wire or Verilog versus SystemVerilog issue. Think about your hardware architecture and solve it that way.

[kgokarn]

Thank you for your reply. I will consider from the synthesis perspective and rewrite the HDL. Thanks again.

[kgokarn]

The issue has been solved. You may close it.

[caryr]

This was not a bug in Icarus.