Error in determine width of the unbased unsized constant '1 in port assignment

[punzik]

Example code:

module mod0 (input [3:0] x);
    initial begin
        $display("%b", x);
        $finish;
    end
endmodule

module test;
    mod0 m ('1);
endmodule

Output:

test.sv:9: warning: Port 1 (x) of mod0 expects 4 bits, got 1.
test.sv:9:        : Padding 3 high bits of the port.
0001

Other simulators (Verilator, Modelsim) and synthesizers (Yosys, Quartus, Vivado) assigns value 'b1111 to port.

[martinwhitaker]

Fixed in both the master and v11 branches.