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steveicarus / iverilog

Icarus Verilog
https://steveicarus.github.io/iverilog/
GNU General Public License v2.0
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Support multidimensional parameters #846

Open catkira opened 1 year ago

catkira commented 1 year ago

Is it correct that iverilog does not support multidimensional parameters like this?

module mod1
#(
    parameter [31:0] PARAM1 [0:2] = '{32'd1, 32'd2, 32'd3}
)
(
    input clk_i
);

I am using version 11.0 (stable) with flag -g2012. It is working with verilator.

martinwhitaker commented 1 year ago

Yes. Parameters having an unpacked array type is a SystemVerilog feature that isn't supported yet.

catkira commented 1 year ago

ok. How hard do You think would it be to implement? I would give it a try if its not too enormous.

catkira commented 1 year ago

@larsclausen told me he is alraedy on it, so I just leave it open until we hear great news 8-)

smunaut commented 1 year ago

Any progress on this ? Just got hit by it ...

Kreijstal commented 4 months ago

Just got hit by this, so here to chime in :)

The error is: error: parameter declared outside parameter port list must have a default value.

Maybe this line of code is relevant https://github.com/steveicarus/iverilog/blob/713b002138e8a55bbb59f507e68e834e7aef92fe/pform.cc#L2913

Kreijstal commented 3 months ago

maybe related #654