Improve performance of OpenCL implementations (manual and PSyclone-generated) for the Xilinx FPGA

stfc / PSycloneBench

Various benchmarks used to inform PSyclone optimisations

BSD 3-Clause "New" or "Revised" License

6 stars 5 forks source link

Improve performance of OpenCL implementations (manual and PSyclone-generated) for the Xilinx FPGA #69

Open sergisiso opened 3 years ago

sergisiso commented 3 years ago

The OpenCL implementation significantly slower in the Xilinx FPGA than a single CPU, the main reason seems to be a serialized interface to access memory through a single memory bank.