search

stffrdhrn / sdram-controller

Verilog SDRAM memory controller
309 stars 94 forks source link

rd_enable latching (or lack of it) #3

Open feldi12 opened 6 years ago

feldi12 commented 6 years ago

Hi! I was going through your code and I noticed, that if the controller is in any of the "REF" states, the busy signal is low. However, when rd_enable signal goes high, the address of read operation will be read and latched, but the rd_enable itself will not start read, as this can only start if the controller is in "IDLE" state. This forces user to leave the address and rd_enable signals high until busy signal goes high, which makes code further on much more complicated. 1) Am I reading it right, or have I missed something? 2) How about latching the rd/wr commands, and supplementing busy signal logic? I think that would solve the problem...

stffrdhrn commented 6 years ago

Hello, thanks for the feedback. It makes sense I can't remember why I didn't do that. Perhaps I was just trying to be lazy or make it more simple?

If you would like to make a patch and test it out it would be great.