For loop confuses the parser

[DavidVentura]

Hi I'm getting unrelated failures when using the vls language server, I've narrowed it down to for loops:

module issue;
        reg [3:0] input_pins_r;
        integer i;
        initial begin
                for(i=0; i<3; i++) begin
                        #1;
                end
                input_pins_r = 0; // <-- This line
        end
endmodule

In the highlighted line, I'm getting Expected token ')', got ';'. This goes away if I delete the for loop. If I delete input_pins_r = 0 then there are no errors either.

There are no changes with for(integer i=0;...

[sthenic]

Hi,

It looks like two things are actually happening here.

1. The parser is yielding a syntax error for i++, which isn't legal Verilog as far as I know. However, I do know that many HDL tools tend to bend the rules a bit and borrow from SystemVerilog (in this case) or introduce new syntax altogether.
2. The error propagation for this particular syntax doesn't appear to work correctly. Instead of the message Expected token '=', got '+', marked for the second + in i++, we get Expected token ')', got ';' marked far from where the syntax error actually happened.

The parsing works if you change i++ to i=i+1.

Unfortunately, I don't have time to fix this right now but I'll leave this task open as a reminder and I'll get to it sooner or later.