stiggy87 / source_to_inst

This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.
10 stars 2 forks source link

What is the runtime for a large file or large list? #10

Open stiggy87 opened 11 years ago

stiggy87 commented 11 years ago

To make this feature better, need to do timing of the function with a large file and a large list?

Test cases:

This is not a requirement for the Milestone, but it will help identify slow parts of the algorithms.