Verilog: If open ( is not on the same line as module, fails

stiggy87 / source_to_inst

This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.

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Verilog: If open ( is not on the same line as module, fails #11

Closed stiggy87 closed 11 years ago

stiggy87 commented 11 years ago

Need to support the case in which the ( is not on the same line as the module definition.